The present invention relates to systems for, and methods of, recovering digitally modulated television signals and, more particularly, to a dual mode QAM/VSB receiver system for recovering quadrature amplitude modulated or vestigial sideband modulated signals.
Modern digital telecommunication systems are operating at ever-increasing data rates to accommodate society""s growing demands for information exchange. However, increasing the data rates, while at the same time accommodating the fixed bandwidths allocated by the Federal Communications Commission (FCC), requires increasingly sophisticated signal processing techniques. Since low cost, small size and low power consumption are portent in the hardware implementations of such communication systems, custom integrated circuit solutions are important to achieving these goals.
Next generation digital television systems, such as cable transported television (CATV) and high-definition television (HDTV) rely on telecommunication transceivers to deliver data at rates in excess of 30 megabits per second (30 Mb/s). The ATSC A/53 Digital Television Standard, was developed by the xe2x80x9cDigital HDTV Alliancexe2x80x9d of U.S. television vendors, and has been accepted as the standard for terrestrial transmission of SDTV and HDTV signals in the United States. The ATSC A/53 standard is based on an 8-level vestigal sideband (8-VSB) modulation format with a nominal payload data rate of 19.4 Mbps in a 6 MHz channel. A high data rate mode, for use in a cable television environment, is also specified by the standard. This particular mode, defined in Annex D to the ITU-T J.83 specification, utilizes a 16-VSB modulation format to provide a data rate of 38.8 Mbps in a 6 MHz channel.
Transmission modes defined in ITU-T J.83 Annex A/C are used primarily outside the United States for digital cable television transmission. The transmission modes supported by this specification have been adopted in Europe as the Digital Video Broadcast for Cable (DVB-C) standard, and further adopted by the Digital Audio-Video Council (DAVIC) with extensions to support 256-QAM modulation formats.
Beyond these divergent requirements, the ITU-T J.83 Annex B standards define the dominant methodology for digital television delivery over CATV networks in the United States. It has been adopted as the physical layer standard by various organizations including the SCTE DVS-031, MCNS-DOCSIS and the IEEE 802.14 committee.
Given the implementation of multiple modulation techniques in the various adopted standards, there exists a need for a television receiver system capable of receiving and demodulating television signal information content that has been modulated and transmitted in accordance with a variety of modulation formats. In particular, such a system should be able to accommodate receipt and demodulation of at least 8 and 16-VSB modulated signals in order to support US HDTV applications, as well as 64 and 256-QAM modulated signals, for European and potential US CATV implementations.
The present invention is directed to digital data communication systems and methods for operating such systems in order to improve the system""s bit error rate in high noise situations. Decision directed adapted equalization, decision directed carrier and/or timing recovery loops are all able to recover significant performance improvements by employing maximum likelihood sequence estimation circuitry to provide a higher percentage of correct symbolic decisions. In particular, such systems are particularly beneficial in the case of U.S. Digital Terrestrial Television Broadcasting applications which employ a trellis coded 8-VSB modulation scheme.
In a first aspect of the invention, an integrated circuit receiver includes decision directed carrier and timing recovery circuits and further includes a decision feedback equalizer. The decision feedback equalizer is constructed with a feedforward filter and a decision feedback filter and incorporates a trellis decoder circuit, coupled to receive symbol samples from the feedforward filter and channel perturbation compensation signals from the decision feedback filter. The trellis decoder circuit is also integrated into the timing loops so as to provide enhanced reliability symbolic decisions to an input of the timing loops.
The trellis decoder includes a decision device, a path metrics module which defines and stores path metrics for a sequential series of symbolic decisions, and a traceback memory module which stores best survivor paths for a sequential series of symbolic decisions. The traceback memory has a length N, the Nth decision representing a final decision and the length N represents a N stage trellis defined path memory, each stage having a time delay characterized by 1/N. A summing circuit is coupled in parallel fashion across the trellis decoder. The summing circuit combines an input symbol, input to the trellis decoder, with a symbolic decision, output from the trellis decoder, to define a sequence estimated error term. A variable delay stage is coupled to delay the input symbol by an amount equal to the delay introduced to an output decision by an action of the trellis decoder.
In a further aspect of the invention, the feedforward filter includes adaptively updateable coefficient taps. The decision feedback filter further includes adaptively updateable coefficient taps. The sequence estimated error term is provided to the feedforward filter and to the decision feedback filter in order to drive the tap updates in a more error free manner.
Increased performance and reliability of both the decision feedback equalizer and timing recovery loops are further achieved by optimizing the tradeoff between trellis decoder symbolic decision delay and symbolic decision reliability. In particular, using decisions closer to the Nth decision increases the reliability of a particular decision. However, increasing delay in a timing recovery loop, by using a symbolic decision closer to the Nth decision, reduces the loop""s bandwidth and tracking ability. Accordingly, various intermediate symbolic decisions, less than the Nth decision, are selectively provided to the various timing recovery loops in order to recover some degree of sequence estimated decision performance with a minimum of delay consequence. Other intermediate symbolic decisions, or a final symbolic decision, is provided to the DFE in order to maximize performance.